Khorami A, Sharifkhani M (2017) Excess power elimination in high resolution dynamic comparators. IEEE Trans Very Large Scale Integr (VLSI) Syst 22(2):343–352 In: Proceedings of IEEE 23rd Iranian Conference Electrical Engineering (ICEE), May 2015, pp 1266–1270īabayan-Mashhadi S, Lotfi R (2014) Analysis and design of a low-voltage low-power double-tail comparator. Rabiei A, Najafizadeh A, Khalafi A, Ahmadi SM (2015) A new ultra low power high speed dynamic comparator. Hassanpourghadi M, Zamani M, Sharifkhani M (2014) A low-power low-offset dynamic comparator for analog to digital converters. Gao J, Li G, Li Q (2015) High-speed low-power common mode insensitive dynamic comparator. In: Proceedings of IEEE Asian Solid State Circuits Conference (A-SSCC), November 2010, pp 1–4 Electron Lett 52(7):509–511Ībbas M, Furukawa Y, Komatsu S, Takahiro JY, Asada K (2010) Clocked comparator for high-speed applications in 65 nm technology. Khorami A, Sharifkhani M (2016) Low-power technique for dynamic comparators. IEEE Trans Circuits Syst II Exp Briefs 53(7):541–545 IEEE J Solid-State Circuits 30(3):166–172įigueiredo PM, Vital JC (2006) Kickback noise reduction techniques for CMOS latched comparators. AEU-Int J Electron Commun 70(7):886–894Ĭho TB, Gray PR (1995) A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. Khorami A, Sharifkhani M (2016) High-speed low-power comparator for analog to digital converters. IEEE Trans Circ Syst II Exp Briefs 62(5):456–460 Ragab K, Chen L, Sanyal A, Sun N (2015) Digital background calibration for pipelined ADCs based on comparator decision time quantization. In: IEEE International Solid-State Circuits Conference (ISSCC) Technical Digital Papers, February 2015, pp 1–3 Hong H-K, et al (2015) A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4 mW 4 × -time-interleaved SAR ADC with a multistep hardware retirement technique. Razavi B, Wooley BA (1992) Design techniques for high-speed, high resolution comparators. Khorami A, Sharifkhani M (2018) A low-power high-speed comparator for precise applications. Index Terms: Analog to digital converter (ADC), static comparator, dynamic comparator, two-stage comparator, low-power, high-speed. The circuit simulations are done by using mentor graphics tool having 250 nm CMOS technology. This design has optimum delay and reduces the excess power consumption. The cross coupled connection in the circuit enhances the amplification gain and reduces the delay. During evaluation phase, after achieving enough pre-amplification gain, the latch is activated. At reset phase, the circuit undergoes discharge state. The circuit operates by specific clock pattern. p-MOS transistors were used as inputs in pre-amplifier and latch. In this paper, a p-MOS latch is present along with a pre-amplifier. Based on the analysis, designer can obtain a new design to trade-off between speed and power. This paper presents the design and analysis of dynamic comparators. The dynamic comparator performance depends on technology that we used. The usage of these dynamic comparators are maximized because of demand for low-power, area efficient and high-speed ADC’s. In the architecture of ADC’s, comparators are the fundamental blocks. In order to convert these analog signals to digital, we need an analog to digital converter (ADC). ![]() The condition of A=B is possible only when all the individual bits of one number exactly coincide with the corresponding bits of another number.įrom the above statements, logical expressions for each output can be expressed as follows.Most of the real world signals have analog behavior. Similarly, the condition for AB can be possible in the following four cases. It consists of eight inputs each for two four-bit numbers and three outputs to generate less than, equal to, and greater than between two binary numbers. The clock used in comparator has a frequency of 1 M Hz. The designs are simulated and studied in 180 nm Technology with Cadence Virtuoso Tool with supply voltage 3.3 V and reference voltage of 3V.
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